Re: CypherPunks: Efficient Hardware DES.

[Brendan Simon <bsimon@ctam.com.au>]

Applied Cryptography (2nd Ed) by Bruce Schneier (Ch 12, page 278).

"The most impressive DES chip is VLSI's 6868 (formely called
"Gatekeeper").  Not only can it perform DES encryption in only 8 clock
cycles (prototypes in the lab can do it in 4 clock cycles), but it also
can do ECB triple DES in 35 clock cycles.  This sounds impossible to me,
too, but I can assure you it works."

The above is a direct extract from the book.  The book is printed in
1996.  I was just wondering if anyone new how the reduction of 16 cycles
to 4 cycles work.  Is it a manipulation of the algorithm or some kind of
pipelining trick ?

Brendan Simon.



James.Wilkins@wdr.com wrote:

> Brendan,
>
> What specific hardware have you heard of that does this? As far as I
> know all our hardware encryptors (usually end to end leased line
> encryptors) all work in 16 cycles. I think another group member,
> Markus Kuhn, while talking about Van Eck phreaking (and the likes)
> said he was able to detect a smart card encrypting data on its chip
> by moitoring its power consumption by a pattern repeated 16 times.
>
> Regards
>
> James
>
> > -----Original Message-----
> > From: bsimon
> > Sent: 12 November 1999 03:53
> > To: cypherpunks
> > Cc: bsimon
> > Subject: FW: CypherPunks: Efficient Hardware DES.
> >
> >
> >
> > I've heard claims of Hardwaere DES being done in 4 clock cycles as
> > apposed to the 16 cycles published in the standard.  Does anyone
> know
> > how this is done ?  Is there any documents or references on a more
> > efficient hardware implementation of the DES algorithm ?  Any other
> > pointers ?